The present invention relates to a method for fabricating a semiconductor device, more specifically to a method for fabricating a semiconductor device comprising the step of etching inter-layer insulation films, etc. by using masks.
The dual damascening, in which an interconnection and via plugs are concurrently formed, can decrease times of burying metals and planarization by CMP (chemical metal polishing), and has a merit of decreasing the interconnecting costs. The dual damascening is widely used in forming multi-interconnection layer structure of semiconductor devices.
A method for forming a multi-interconnection layer structure by the conventional dual damascening will be explained with reference to FIGS. 12A-12B to 17A-17B. FIGS. 12A-12B to 17A-17B are sectional views of the multi-interconnection layer structure in the steps of the method for forming the multi-interconnection layer structure, which explain the method. The method will be explained by means of an example in which a via layer connected to a first interconnection layer which is the first layer, and a second interconnection layer are formed.
First, the structure of the first layer, which is the first interconnection layer, will be explained with reference to FIG. 12A.
A Transistor including a gate electrode 102 and source/drain diffused layers 104 are formed on a silicon substrate 100.
An inter-layer insulation film 108 of USG (undoped silicate glass) is formed on the silicon substrate 100 with the transistor formed on. A contact hole 110 is formed in the inter-layer insulation film 108 down to the source/drain diffused layer 104. A conductor plug 112 of tungsten (W) is buried in the contact hole 110.
In the inter-layer insulation film 108, a first interconnection groove 114 having a first layer interconnection pattern connected to the conductor plug 112 is formed. A tantalum nitride (TaN) film 116 is formed on the inside surface and the bottom surface of the first interconnection groove 114, and the first interconnection layer 118 of Cu is buried in the first interconnection groove 14 with the TaN film 116 formed on.
A SiN film 120 is formed on the entire surface of the inter-layer insulation film 108 with the first interconnection layer 118 buried in.
Then, the step of forming a via layer and a second interconnection layer connected to the above-described first interconnection layer 118 will be explained.
First, on the SiN film 120, an inter-layer insulation film 122 of USG, a SiN film 124, an inter-layer insulation film 126 of USG and a SIN film 128 are formed (FIG. 12B).
Then, on the SiN film 128, an ARC (anti-reflection coating) 130 of a silicon nitride oxide (SiON) film for patterning a resist film, and a resist film 134 are sequentially formed.
Next, an opening for exposing a region for a via hole 132 to be formed in is formed in the resist film 134 by photolithography (FIG. 13A).
Then, with the resist film 134 with the opening formed in as a mask and with the SiN film 124 as an etching stopper, the anti-reflection coating 130, the SiN film 128 and the inter-layer insulation film 126 are etched.
After the etching, the resist film 134 is removed by ashing using, e.g., oxygen plasmas (FIG. 13B).
Next, a resist film 136 is formed on the entire surface, and an opening for exposing a region for the second interconnection groove 138 to be formed in the resist film 136 by photolithography (FIG. 14A).
Then, with the resist film 136 with the opening formed in as a mask, the anti-reflection coating 130, and the SiN film 128 are etched. The SiN film 128 as a mask for forming the via hole 132 and the second interconnection groove 138 is thus patterned. Concurrently therewith, the SiN film 124 which is used as the etching stopper and exposed by etching the inter-layer insulation film 126 is also etched. After the etching has completed, the resist film 136 is removed by ashing using, e.g., oxygen plasmas (FIG. 14B).
Next, with the SiN film 128 as a mask and with the SiN films 124, 120 as an etching stopper, the inter-layer insulation films 126, 122 are etched. Concurrently therewith, the anti-reflection coating 130 of the SiON film is etched (FIG. 15A).
Next, the SiN films 124, 120 which are used as the etching stopper and exposed by etching the inter-layer insulation films 126, 122 are etched. The via hole 132 down to the first interconnection layer 118, and the second interconnection groove 138 are thus formed (FIG. 15B).
Then, a TaN film 140 is formed on the entire surface. Next, the TaN film 140 except that formed on the inside surface and the bottom of the second interconnection groove 138 and the via hole 132 is removed by CMP (FIG. 16A).
Next, a Cu film (not shown) is formed on the entire surface by, e.g., sputtering. Then, with the Cu film formed by sputtering as a seed layer, a Cu film 142 is formed by plating (FIG. 16B).
Then, the Cu film 142 is polished by CMP until the surface of the inter-layer insulation film 126 is exposed. Thus, the via layer 144 and the second interconnection layer 146 of the same Cu film 142 are formed in the via hole 132 and the second interconnection groove 138 (FIG. 17A).
Next, a SiN film 148 is formed on the entire surface as a diffusion preventing film for preventing the diffusion of the Cu (FIG. 17B).
Hereafter, in accordance with a structure of a semiconductor device to be fabricated, the above-described steps are repeated to thereby form a multi-interconnection layer structure comprising a plurality of interconnection layers is fabricated.
However, the above-described conventional method for fabricating a semiconductor device has the following disadvantages when a SiN film is used as a mask for etching the inter-layer insulation film of USG or others to thereby form the via hole and the interconnection groove.
First, in etching the inter-layer insulation film of USG or others, the etching selective ratio of the SiN film used as a mask is not enough. When the via hole and the interconnection groove are etched, pattern dimensions on the mask often become larger than pattern dimensions on the resist film.
The SiN film must be formed considerably thick so that the SiN film can function as a mask. Resultantly, even when the SiN film on the bottom of the via hole, which has been used as the etching stopper, has been removed by etching, as shown in FIG. 15B, the SiN film of the upper layer used as the mask often remains. Because of such residue of the SiN film used as the mask, an effective dielectric constant between the layers is often increased.